TM4C1233D5PZ Datasheet, PDF (532/1242 Pages) Texas Instruments – Tiva Microcontroller

Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the Flash memory controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PROGMASK reserved ERMASK INVDMASK VOLTMASK
reserved
EMASK PMASK AMASK
Type RO
RO
RW
RO
RW
RW
RW
RO
RO
RO
RO
RO
RO
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:14
13
Name
reserved
PROGMASK
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PROGVER Interrupt Mask
Value Description
0 The PROGRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the PROGRIS
bit is set.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
ERMASK
RW
0
ERVER Interrupt Mask
Value Description
0 The ERRIS interrupt is suppressed and not sent to the interrupt
controller.
1 An interrupt is sent to the interrupt controller when the ERRIS
bit is set.
10
INVDMASK
RW
0
Invalid Data Interrupt Mask
Value Description
0 The INVDRIS interrupt is suppressed and not sent to the
interrupt controller.
1 An interrupt is sent to the interrupt controller when the INVDRIS
bit is set.
532
June 12, 2014
Texas Instruments-Production Data