TM4C1233D5PZ Datasheet, PDF (383/1242 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233D5PZ Microcontroller
Register 93: Controller Area Network Deep-Sleep Mode Clock Gating Control
(DCGCCAN), offset 0x834
The DCGCCAN register provides software the capability to enable and disable the CAN modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the CAN modules. To support
legacy software, the DCGC0 register is available. A write to the DCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC0 register can be read back correctly with a read of the DCGC0 register. If software
uses this register to write a legacy peripheral (such as CAN0), the write causes proper
operation, but the value of that bit is not reflected in the DCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN)
Base 0x400F.E000
Offset 0x834
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
D0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
D0
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0 CAN module 0 is disabled.
1 Enable and provide a clock to CAN module 0 in deep-sleep
mode.
June 12, 2014
383
Texas Instruments-Production Data