TM4C1233D5PZ Datasheet, PDF (398/1242 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 104: Synchronous Serial Interface Peripheral Ready (PRSSI), offset
0xA1C
The PRSSI register indicates whether the SSI modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCSSI bit is changed. A reset change is initiated if the
corresponding SRSSI bit is changed from 0 to 1.
The PRSSI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Synchronous Serial Interface Peripheral Ready (PRSSI)
Base 0x400F.E000
Offset 0xA1C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
R3
R2
R1
R0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
R3
Type
RO
RO
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Module 3 Peripheral Ready
Value Description
0 SSI module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 3 is ready for access.
2
R2
RO
0
SSI Module 2 Peripheral Ready
Value Description
0 SSI module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 2 is ready for access.
1
R1
RO
0
SSI Module 1 Peripheral Ready
Value Description
0 SSI module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1 SSI module 1 is ready for access.
398
June 12, 2014
Texas Instruments-Production Data