SBAS052 Datasheet, PDF (9/17 Pages) Texas Instruments – Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE

Not Recommended For New Designs
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a “HIGH” level on bit 0 will cause the output
to be muted (this is ramped down in the digital domain, so
no “click” is audible). Bit 1 is used to control de-emphasis.
A “LOW” level on bit 1 disables de-emphasis, while a
“HIGH” level enables de-emphasis.
Bit 2, (OPE) is used for operational control. Table IV
illustrates the features controlled by OPE.
OPE = 1
OPE = 0
DATA INPUT
Zero
Other
Zero
Other
DAC OUTPUT
Forced to BPZ⁽¹⁾
Forced to BPZ⁽¹⁾
Controlled by IZD
Normal
SOFTWARE MODE
INPUT
Enabled
Enabled
Enabled
Enabled
TABLE IV. Output Enable (OPE) Function.
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65, 536 cycles of BCKIN,
the output will be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
IZD = 1
IZD = 0
DATA INPUT
Zero
Other
Zero
Other
DAC OUTPUT
Forced to BPZ⁽¹⁾
Normal
Zero⁽²⁾
Normal
TABLE V. Infinite Zero Detection (IZD) Function.
DATA INPUT
DAC OUTPUT
RSTB = “HIGH”
RSTB = “LOW”
Zero
Other
Zero
Other
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ⁽¹⁾
Forced to BPZ⁽¹⁾
SOFTWARE
MODE
INPUT
Enabled
Enabled
Disabled
Disabled
TABLE VI. Reset (RSTB) Function.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to
output amplifier.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1720 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
Bit 4 (IW1)
0
0
1
0
Bit 3 (IW0)
0
1
0
0
Input Resolution
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1720 can be programmed for 16 different
states, as shown in Table VII.
PL0 PL1 PL2 PL3 Lch OUTPUT
0
0
0
0
MUTE
0
0
0
1
MUTE
0
0
1
0
MUTE
0
0
1
1
MUTE
0
1
0
0
R
0
1
0
1
R
0
1
1
0
R
0
1
1
1
R
1
0
0
0
L
1
0
0
1
L
1
0
1
0
L
1
0
1
1
L
1
1
0
0
(L + R)/2
1
1
0
1
(L + R)/2
1
1
1
0
(L + R)/2
1
1
1
1
(L + R)/2
Rch OUTPUT
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
NOTE
MUTE
REVERSE
STEREO
MONO
TABLE VII. Programmable Output Format.
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 IZD SF1 SF0 res res res ATC LRP I²S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency and infinite zero detection.
Bits 0 (I²S) and 1 (LRP) are used to control the input data
format. A “LOW” on bit 0 sets the format to “Normal”
(MSB-first, right-justified Japanese format) and a “HIGH”
sets the format to I²S (Philips serial data protocol). Bit 1
(LRP) is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is “LOW”, left channel data is assumed
when LRCIN is in a “HIGH” phase and right channel data
is assumed when LRCIN is in a “LOW” phase. When bit
1 is “HIGH”, the polarity assumption is reversed.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is “HIGH”, the attenuation data loaded in program
Register 0 is used for both left and right channels. When
bit 2 is “LOW”, the attenuation data for each register is
applied separately to left and right channels.
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency:
SF1 SF0
0
0
0
1
1
0
1
1
Sampling Frequency
44.1kHz group
48kHz group
32kHz group
Reserved
22.05/44.1/88.2kHz
24/48/96kHz
16/32/64kHz
Not Defined
Bit 8 is used to control the infinite zero detection function
(IZD).
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PCM1720