SBAS052 Datasheet, PDF (7/17 Pages) Texas Instruments – Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE

Not Recommended For New Designs
TYPICAL CONNECTION DIAGRAM
Figure 4 illustrates the typical connection diagram for
PCM1720 used in a stand-alone application.
SYSTEM CLOCK
The system clock for PCM1720 must be either 256f_S or
384f_S, where f_S is the audio sampling frequency (LRCIN),
typically 32kHz, 44.1kHz or 48kHz. The system clock is
used to operate the digital filter and the noise shaper. The
system clock input (SCKI) is at pin 2.
PCM1720 has a system clock detection circuit which auto-
matically detects the frequency, either 256f_S or 384f_S. The
system clock should be synchronized with LRCIN (pin 16),
but PCM1720 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater
than ±6 bit clocks (BCKIN), the synchronization is per-
formed automatically. The analog outputs are forced to a
bipolar zero state (V_CC/2) during the synchronization func-
tion. Table I shows the typical system clock frequency
inputs for the PCM1720.
SAMPLING
RATE (LRCIN)
32kHz
44.1kHz
48kHz
SYSTEM CLOCK
FREQUENCY (MHz)
256f_S
8.192
384f_S
12.288
11.2896
16.9340
12.288
18.432
TABLE I. System Clock Frequencies vs Sampling Rate.
SPECIAL FUNCTIONS
PCM1720 includes several special functions, including digi-
tal attenuation, digital de-emphasis, soft mute, data format
selection and input word resolution. These functions are
controlled using a three-wire interface. MD (pin 6) is used
for the program data, MC (pin 5) is used to clock in the
program data, and ML (pin 4) is used to latch in the program
data. Table II lists the selectable special functions.
FUNCTION
Input Audio Data Format Selection
Normal Format
I²S Format
Input Audio Data Bit Selection
16/20/24 Bits
Input LRCIN Polarity Selection
Lch/Rch = High/Low
Lch/Rch = Low/High
De-emphasis Control
Soft Mute Control
Attenuation Control
Lch, Rch Individually
Lch, Rch Common
Infinite Zero Detection Circuit Control
Operation Enable (OPE)
Sample Rate Selection
Internal System Clock Selection
256f_S
384f_S
Sampling Frequency
44.1kHz Group
48kHz Group
32kHz Group
Analog Output Mode
L, R, Mono, Mute
TABLE II. Selectable Functions.
DEFAULT MODE
Normal Format
16 Bits
Lch/Rch = High/Low
OFF
OFF
0dB
Lch, Rch Individually Fixed
OFF
Enabled
384f_S
44.1kHz
Stereo
PCM
Audio Data
Processor
15
14
16
2
256f_S/384f_S CLK
+5V Analog
20
19
DGND
DIN
BCKIN
LRCIN
V_DD
12
V_OUTL _{13 200Ω}
CAP
+
10µF
SCKI
V_OUTR ⁹
PCM1720
8
ZERO
Post
LPF
Post
LPF
Analog
Mute
Analog
Mute
AGND
10
ML
MC
MD
RSTB
V_CC
11
4
5
6
7
+5V Analog
STRB
SCKO System
SDO ^Controller
PIO
Lch Analog Out
Rch Analog Out
FIGURE 4. Typical Connection Diagram.
7
®
PCM1720