LP3470 Datasheet, PDF (9/22 Pages) National Semiconductor (TI) – Tiny Power On Reset Circuit

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Feature Description (continued)
LP3470
SNVS003G – JUNE 1999 – REVISED APRIL 2016
Figure 9. Reset Output Timing Diagram
7.3.3 Pullup Resistor Selection
The Reset output structure of the LP3470 is a simple open-drain N-channel MOSFET switch. A pullup resistor
(R₁) must be connected to V_CC.
R₁ must be large enough to limit the current through the output MOSFET (Q₁) below 10 mA. A resistor value of
more than 680 Ω ensures this. R₁ must also be small enough to ensure a logic high while supplying all the
leakage current through the Reset pin. A resistor value of less than 68 kΩ satisfies this condition. A typical pullup
resistor value of 20 kΩ is sufficient in most applications.
7.3.4 Negative-Going V_CC Transients
The LP3470 is relatively immune to short duration negative-going V_CC transients (glitches). The Typical
Characteristics show the maximum transient duration versus negative transient amplitude (see Figure 6), for
which reset pulses are not generated. This graph shows the maximum pulse width a negative-going V_CC
transient may typically have without causing a reset pulse to be issued. As the transient amplitude increases (in
other words, goes farther below the reset threshold), the maximum allowable pulse width decreases. A 0.1-µF
bypass capacitor mounted close to V_CC provides additional transient immunity.
7.4 Device Functional Modes
7.4.1 Reset Output Low
When the V_CC supply voltage is below a threshold (V_RTH) voltage minus a hysteresis (V_HYST) voltage, the Reset
pin will output logic low. Reset is ensured to be a logic low for V_CC > 0.5 V.
7.4.2 Reset Output High
When the V_CC supply voltage exceeds the reset threshold, the Reset is kept asserted for a time period (t_RP)
programmed by an external capacitor (C₁); after this interval Reset goes to logic high.
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