LP3470 Datasheet, PDF (8/22 Pages) National Semiconductor (TI) – Tiny Power On Reset Circuit

LP3470
SNVS003G – JUNE 1999 – REVISED APRIL 2016
7 Detailed Description
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7.1 Overview
The LP3470 micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in
microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold
on the V_CC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted
and remains asserted for an interval programmed by an external capacitor after V_CC has risen above the
threshold voltage. The reset threshold options are 2.63 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V.
7.2 Functional Block Diagram
SRT
V_CC
V_CC1
LP3470
V_REF
R_A
+
_
R_B
Q_A
DELAY
Reset
GND
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7.3 Feature Description
7.3.1 Reset Time-Out Period
The reset time-out period (t_RP) is programmable using an external capacitor (C₁) connected to pin SRT of
LP3470. A ceramic chip capacitor rated at or above 10 V is sufficient. The reset time-out period (t_RP) can be
calculated using Equation 1.
t_RP (ms) = 2000 x C₁ (µF)
(1)
For example a C₁ of 100 nF will achieve a t_RP of 200 ms. If no delay due to t_RP is needed in a certain application,
the pin SRT must be left floating.
7.3.2 Reset Output
In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power
down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from
occurring.
The LP3470 asserts a reset signal whenever the V_CC supply voltage is below a threshold (V_RTH) voltage. Reset is
ensured to be a logic low for V_CC > 0.5 V. Once V_CC exceeds the reset threshold, the reset is kept asserted for a
time period (t_RP) programmed by an external capacitor (C₁); after this interval Reset goes to logic high. If a
brownout condition occurs (monitored voltage falls below the reset threshold minus a small hysteresis), Reset
goes low. When V_CC returns above the reset threshold, Reset remains low for a time period t_RP before going to
logic high. Figure 9 shows this behavior.
8
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