DS99R124Q_15 Datasheet, PDF (9/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124Q
www.ti.com
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
Recommended Timing for the Serial Control Bus (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_SU:STA Set Up time for a start or a
Standard Mode
4.7
repeated start condition,
Figure 13
Fast Mode
0.6
t_HD;DAT Data Hold Time,
Standard Mode
0
Figure 13
Fast Mode
0
t_SU;DAT Data Set Up Time,
Standard Mode
250
Figure 13
Fast Mode
100
t_SU;STO Set Up Time for STOP
Standard Mode
4.0
Condition, Figure 13
Fast Mode
0.6
t_BUF
Bus Free Time
Standard Mode
4.7
Between STOP and START,
Figure 13
Fast Mode
1.3
t_r
SCL & SDA Rise Time,
Figure 13
Standard Mode
Fast Mode
t_f
SCL & SDA Fall Time,
Figure 13
Standard Mode
Fast mode
Typ
Max Units
us
us
3.45
us
0.9
us
ns
ns
us
us
us
us
1000 ns
300
ns
300
ns
300
ns
DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
V_IH
Input High Level
SDA and SCL
V_IL
Input Low Level Voltage
SDA and SCL
V_HY
V_OL
I_in
t_R
t_F
t_SU;DAT
t_HD;DAT
t_SP
C_in
Input Hysteresis
SDA RiseTime – READ
SDA Fall Time – READ
Set Up Time — READ
Hold Up Time — READ
Input Filter
Input Capacitance
SDA, I_OL = +0.5 mA
SDA or SCL, Vin = V_DDIO or GND
SDA, RPU = X, Cb ≤ 400pF
SDA or SCL
Min
0.7*
V_DDIO
GND
0
-10
500
580
Typ
Max Units
V_DDIO
V
0.3*
V_DDIO
V
>50
mV
0.36
V
+10
µA
850
ns
120
ns
ns
ns
50
ns
<5
pF
AC Timing Diagrams and Test Circuits
TxCLKOUT
TxOUT[odd]
TxOUT[even]
Cycle N
Cycle N+1
Figure 4. Checkerboard Data Pattern
+V_OD
-V_OD
+V_OD
-V_OD
+V_OD
-V_OD
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