DS99R124Q_15 Datasheet, PDF (19/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

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DS99R124Q
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
BISTEN
(SER)
BISTEN
(DES)
PCLK
(RFB = L)
RGB[7:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
DATA
X
(internal)
PASS
w/ BISTM = L
Prior Result
DATA
X
(internal)
PASS
w/ BISTM = H
Prior Result
Normal
PRBS
X = bit error(s)
X
X
X = bit error(s)
X
X
BIST Test
BIST Duration
Figure 21. BIST Waveforms
PASS
FAIL
FAIL
BIST
Result
Held
Normal
Serial Bus Control — Optional
The DS99R124 may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 22.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V_DDIO. For most
applications a 4.7 k pull up resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
HOST
SCL
SDA
V_DDIO
4.7k
4.7k
10k
ID[X]
R_ID
SER
or
SCL _DES
SDA
To Other
Devices
Figure 22. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to V_DD (1.8V, NOT V_DDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
V_DD1.8V, NOT V_DDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 5 for the Des.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 23
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