DS99R124Q_15 Datasheet, PDF (23/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124Q
www.ti.com
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS99R124Q, in conjunction with the DS99R421Q or DS90UR241Q, is intended for interfacing between a
host (graphics processor) and a Display. It supports an 18-bit color depth (RGB666) and up to WVGA display
formats. In a RGB666 application, 18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 43MHz.
TYPICAL APPLICATION CONNECTION
Figure 26 shows a typical application of the DS99R124QQ Des in pin mode for a 43 MHz WVGA Display
Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver provides internal
termination. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
1.8V
FB1
C3
FB2
C4
DS99R124Q (CON)
VDDL
VDDTX
VDDL
VDDA
VDDA
VDDIO
3.3V
FB4
C7
VDDIO
FB5
C8
FB3
C5
VDDP
VDDP
VDDIO
C9
C1
Serial
FPD-Link II
Interface
C2
Host
Control
R
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C12 = 4.7 PF
C13 = > 10 PF
R = 10 k:
FB1 - FB5: Impedance = 1 k:
Low DC resistance (< 1:)
VDDP
C6
RIN+
RIN-
CMF
C10
BISTEN
BISTM
OE
PDB
C13
SCL
SDA
ID[X]
NC
2
8
GND
DAP (GND)
TxCLKOUT+
TxCLKOUT
-
TxOUT2+
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
OS[2]
OS[1]
OS[0]
LOCK
PASS
VODSEL
OSS_SEL
LFMODE
SSC[2]
SSC[1]
SSC[0]
Tie to
desired
setting
FPD-Link
Interface
LVDS
100 Ohm
Termination
Figure 26. DS99R124Q Typical Connection Diagram — Pin Control
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