DS15MB200_13 Datasheet, PDF (9/18 Pages) Texas Instruments – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

DS15MB200
www.ti.com
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
TRI-STATE AND POWERDOWN MODES
The DS15MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows
each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is
useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active
while some are in TRI-STATE.
When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a
Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is
essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators.
When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the
outputs because of the ramp to power up the internal bandgap reference generators.
Any single output enable that remains active will hold the device in active mode even if the other five outputs are
in TRI-STATE.
When in Powerdown mode, any output enable that becomes active will wake up the device back into active
mode, even if the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal
circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051) for more
information.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.
This drives a pair of emitter-followers that require a 50 ohm to V_CC-2.0 load. A modern LVPECL driver will
typically include the termination scheme within the device for the emitter follower. If the driver does not include
the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB,
therefore, a load scheme without a unique power supply requirement may be used.
50:
LVPECL
50:
R1 R2
150: 150:
15MB200
Figure 8. DC Coupled LVPECL to LVDS Interface
Figure 8 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for
the driver emitter followers, and may be included as part of the driver device⁽¹⁾. The DS15MB200 includes a 100
ohm input termination for the transmission line. The common mode voltage will be at the normal LVPECL
levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage,
V_CM, range. Most Texas Instrument's LVDS receivers have wide V_CM range. The exceptions are noted in devices’
respective datasheets. Those LVDS devices that do have a wide V_CM range do not vary in performance
significantly when receiving a signal with a common mode other than standard LVDS V_CM of 1.2 V.
(1) The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL
driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS15MB200