DS15MB200_13 Datasheet, PDF (7/18 Pages) Texas Instruments – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

DS15MB200
www.ti.com
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
t_JIT
Jitter (0% Pre-emphasis)⁽⁵⁾
Conditions
Min
RJ - Alternating 1 and 0 at 750MHz⁽⁶⁾
DJ - K28.5 Pattern, 1.5 Gbps⁽⁷⁾
TJ - PRBS 2⁷-1 Pattern, 1.5 Gbps⁽⁸⁾
t_ON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to active.
t_ON2
LVDS Output Enable Time from
Time from ENA_n, ENB_n, or ENL_n to
Powerdown Mode
OUT± change from Powerdown Mode to
active.
t_OFF
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE
or Powerdown mode.
Typ ⁽¹⁾
1.1
20
14
0.5
10
Max
Units
1.5
psrms
34
psp-p
28
psp-p
1.5
µs
20
µs
12
ns
(5) Jitter is not production tested, but guaranteed through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50%
duty cycle at 750MHz, t_r = t_f = 50ps (20% to 80%).
(7) Deterministic Jitter, or D_J, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been
subtracted. The input voltage = V_ID = 500mV, K28.5 pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
(8) Total Jitter, or T_J, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been
subtracted. The input voltage = V_ID = 500mV, 2⁷-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%).
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