DS15MB200_13 Datasheet, PDF (6/18 Pages) Texas Instruments – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

DS15MB200
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
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Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n)
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
I_IH
High Level Input Current
V_IN = V_DD = V_DDMAX
I_IHR
High Level Input Current
PREA_n, PREB_n, PREL_n
I_IL
Low Level Input Current
V_IN = V_SS, V_DD = V_DDMAX
C_IN1
Input Capacitance
Any Digital Input Pin to V_SS
C_OUT1 Output Capacitance
Any Digital Output Pin to V_SS
V_CL
Input Clamp Voltage
I_CL = −18 mA
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
V_TH
Differential Input High Threshold⁽²⁾ V_CM = 0.8V or 1.2V or 3.55V,
V_DD = 3.6V
V_TL
Differential Input Low Threshold⁽²⁾ V_CM = 0.8V or 1.2V or 3.55V,
V_DD = 3.6V
V_ID
Differential Input Voltage
V_CM = 0.8V to 3.55V, V_DD = 3.6V
V_CMR
Common Mode Voltage Range
V_ID = 150 mV, V_DD = 3.6V
C_IN2
Input Capacitance
IN+ or IN− to V_SS
I_IN
Input Current
V_IN = 3.6V, V_DD = V_DDMAX or 0V
V_IN = 0V, V_DD = V_DDMAX or 0V
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
2.0
GND
−10
40
−10
−1.5
−100
100
0.05
−15
−15
V_OD
Differential Output Voltage,
0% Pre-emphasis⁽²⁾
R_L is the internal 100Ω between OUT+
and OUT−
250
ΔV_OD
V_OS
ΔV_OS
Change in V_OD between
Complementary States
Offset Voltage⁽³⁾
Change in V_OS between
Complementary States
-35
1.05
-35
I_OS
C_OUT2
Output Short Circuit Current
Output Capacitance
OUT+ or OUT− Short to GND
OUT+ or OUT− to GND when TRI-
STATE
SUPPLY CURRENT (Static)
I_CC
Supply Current
All inputs and outputs enabled and
active, terminated with external load of
100Ω between OUT+ and OUT-.
I_CCZ
Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0 = ENA_1 =
ENB_1 = ENL_1 = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200
Time
Mb/s, measure between 20% and 80% of
t_HLT
Differential High to Low Transition
V_OD. ⁽⁴⁾
Time
t_PLHD
t_PHLD
t_SKD1
t_SKCC
Differential Low to High Propagation
Delay
Differential High to Low Propagation
Delay
Pulse Skew
Output Channel to Channel Skew
Use an alternating 1 and 0 pattern at 200
Mb/s, measure at 50% V_OD between
input to output.
|t_PLHD–t_PHLD| ⁽⁴⁾
Difference in propagation delay (t_PLHD or
t_PHLD) among all output channels.⁽⁴⁾
Typ ⁽¹⁾
2.0
4.0
−0.8
0
0
2.0
360
1.22
−21
4.0
225
0.6
170
170
1.0
1.0
25
50
Max
V_DD
0.8
+10
200
+10
Units
V
V
µA
µA
µA
pF
pF
V
100
mV
mV
2400
mV
3.55
V
pF
+15
µA
+15
µA
500
mV
35
mV
1.475
V
35
mV
-40
mA
pF
275
mA
4.0
mA
250
ps
250
ps
2.5
ns
2.5
ns
75
ps
115
ps
(1) Typical parameters are measured at V_DD = 3.3V, T_A = 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
(3) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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