DRV8803_16 Datasheet, PDF (9/26 Pages) Texas Instruments – Quad Low-Side Driver IC

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DRV8803
SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
Feature Description (continued)
7.3.2 Protection Circuits
The DRV8803 device is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.2.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the t_OCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the t_RETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and reapplied.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
7.4 Device Functional Modes
7.4.1 Parallel Interface Operation
The DRV8803 device is controlled with a simple parallel interface. Logically, the interface is shown in Figure 6.
nENBL
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
Figure 6. Parallel Interface Operation
7.4.2 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. Note that
nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic. All inputs are ignored while RESET is active. Note
that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive
RESET at power up.
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