DRV8803_16 Datasheet, PDF (13/26 Pages) Texas Instruments – Quad Low-Side Driver IC

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10 Layout
DRV8803
SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I² × R_DS(on) heat that is generated in the device.
10.2 Layout Example
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
nFA ULT
NC
IN1
IN2
GND
IN3
IN4
RESET
Figure 13. Recommended Layout
10.3 Thermal Consideration
10.3.1 Thermal Protection
The DRV8803 device has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.2 Power Dissipation
Power dissipation in the DRV8803 device is dominated by the power dissipated in the output FET resistance, or
R_DS(on). Average power dissipation of each FET when running a static load can be roughly estimated by
Equation 2:
P = R_DS(ON) · (I_OUT)²
where
• P is the power dissipation of one FET
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