DRV10964 Datasheet, PDF (9/27 Pages) Texas Instruments – Three-Phase Sinusoidal Sensorless BLDC Motor Driver

www.ti.com
DRV10964
SLDS227 – MARCH 2016
Feature Description (continued)
The duty cycle of PWM input is converted into a 9-bit digital number (from 0 to 511). The control resolution is
1/512 ≈ 0.2%. The duty cycle analyzer implements a first order transfer function between the input duty cycle and
the 9-bit digital number. This is illustrated in Figure 4 and Figure 5.
PWM In
9-bit Digital
Number
Amplitude of Output
Sin-wave
PWM Output
Duty Cycle Analyzer
AVS
Figure 4. PWM Command Input Controls the Output Peak Amplitude
50%
255
(511 is the Maximum)
255
No AVS or Software
Current Limit Occurs
VCC/2
50%
Output at Peak
Figure 5. Example of PWM Command Input Controlling the Output
The transfer function between the PWM commanded duty cycle and the output peak amplitude is adjustable in
the DRV10964 device. The output peak amplitude is described by Equation 1 when PWM_dc > minimum operation
duty cycle. The minimum operation duty cycle is 10%. When the PWM commanded duty cycle is lower than
minimum operation duty cycle and higher than 0.38%, the output will be controlled at the minimum operation duty
cycle. When the input duty cycle is lower than 0.38%, the DRV10964 device will not drive the output, and enters
the standby mode. This is illustrated in Figure 6.
Output Duty
10%
0
10%
Input Duty
Minimum Duty Cycle = 10%
Figure 6. Speed Control Transfer Function
7.3.3 Motor Direction Change
The DRV10964 can be easily configured to drive the motor in either direction by setting the input on the FR
(Forward Reverse) pin to a logic 1 or logic 0 state. The direction of commutation as described by the
commutation sequence is illustrated in Table 1.
Motor direction
Table 1. Motor Direction Phase Sequencing
FR = 0
U->V->W
FR = 1
U->W->V
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DRV10964
Submit Documentation Feedback
9