DAC121C085CIMM Datasheet, PDF (9/34 Pages) Texas Instruments – 12-Bit Micro Power Digital-to-Analog Converter

DAC121C081, DAC121C085
www.ti.com
SNAS395D – DECEMBER 2007 – REVISED MARCH 2013
A.C. and Timing Characteristics (continued)
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V_A = +2.7V to +5.5V, V_REF = V_A, R_L = Infinity, C_L = 200 pF to GND. Boldface limits
apply for T_MIN ≤ T_A ≤ T_MAX and all other limits are at T_A = 25°C, unless otherwise specified.
Symbol
Parameter
Conditions ⁽¹⁾
Typical⁽²⁾ Limits⁽¹⁾⁽²⁾
Units
(Limits)
Standard Mode
300
ns (max)
t_fCL
Fall time of a SCL signal
Fast Mode
High Speed Mode, C_b = 100pF
20+0.1C_b
300
10
40
ns (min)
ns (max)
ns (min)
ns (max)
High Speed Mode, C_b = 400pF
20
ns (min)
80
ns (max)
C_b
Capacitive load for each bus line (SCL
and SDA)
400
pF (max)
t_SP
Pulse Width of spike suppressed⁽⁵⁾⁽⁶⁾
Fast Mode
High Speed Mode
50
ns (max)
10
ns (max)
t_outz
SDA output delay (see the
ADDITIONAL TIMING INFORMATION:
toutz section)
Fast Mode
High Speed Mode
87
270
ns (max)
38
60
ns (max)
(5) Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for
hs-mode.
(6) This parameter is specified by design and/or characterization and is not tested in production.
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