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DAC121C085CIMM Datasheet, PDF (3/34 Pages) Texas Instruments – 12-Bit Micro Power Digital-to-Analog Converter
DAC121C081, DAC121C085
www.ti.com
Symbol
VOUT
VA
GND
SDA
Type
Analog Output
Supply
Ground
Digital
Input/Output
SCL
ADR0
Digital Input
Digital Input,
three levels
ADR1
Digital Input,
three levels
VREF
PAD
(LLP only)
Supply
Ground
SNAS395D – DECEMBER 2007 – REVISED MARCH 2013
PIN DESCRIPTIONS
Equivalent Circuit
Description
Analog Output Voltage.
Power supply input. For the SOT and WSON versions, this
supply is used as the reference. Must be decoupled to GND.
Ground for all on-chip circuitry.
PIN
Snap D1
Back
GND
Serial Data bi-directional connection. Data is clocked into or
out of the internal 16-bit register relative to the clock edges
of SCL. This is an open drain data line that must be pulled
to the supply (VA) by an external pull-up resistor.
Serial Clock Input. SCL is used together with SDA to control
the transfer of data in and out of the device.
V+
PIN
D1
2.1k
41.5k
Snap
Back
41.5k
GND
Tri-state Address Selection Input. Sets the two Least
Significant Bits (A1 & A0) of the 7-bit slave address. (see
Table 1)
Tri-state Address Selection Input. Sets Bits A6 & A3 of the
7-bit slave address. (see Table 1)
Unbufferred reference voltage. For the VSSOP, this supply
is used as the reference. VREF must be free of noise and
decoupled to GND.
Exposed die attach pad can be connected to ground or left
floating. Soldering the pad to the PCB offers optimal thermal
performance and enhances package self-alignment during
reflow.
Package Pinouts
SOT
VOUT
VA
GND
SDA
SCL
ADR0
ADR1
VREF PAD (WSON only)
1
2
3
4
5
6
N/A
N/A
N/A
WSON
6
5
4
3
2
1
N/A
N/A
7
VSSOP
8
6
5
4
3
1
2
7
N/A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2007–2013, Texas Instruments Incorporated
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