BQ4802LYPW Datasheet, PDF (9/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR AND EXTERNAL SRAM NONVOLATILE MEMORY BACKUP

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bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WRITE CYCLE (T_A = T_OPR, V_CC = 5 V)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
tWC Write cycle time
200
ns
tCW Chip select to end of write
See Note 1
195
ns
tAW
tAS
tWP
tWR1
tWR2
Address valid to end of write
Address setup time
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
See Note 1
Measured from address valid to beginning of write(2)
Measured from beginning of write to end of write(1)
Measured from WE going high to end of write cycle(3)
Measured from CS going high to end of write cycle(3)
195
ns
30
ns
165
ns
5
ns
15
ns
tDW
tDH1
tDH2
tWZ
tOW
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enable to output high Z
Output active from end of write
Measured to first low-to-high transition of either CS or WE
Measured from WE going high to end of write cycle(4)
Measured from CS going high to end of write cycle(4)
I/O pins are in output state.(5)
I/O pins are in output state.(5)
50
ns
0
ns
10
ns
0
45 ns
0
ns
(1) _{A write cycle ends at the earlier transition of CS going high and WE going high.}
(2) _{A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.}
(3) _{Either tWR1 or tWR2 must be met.}
(4) _{Either tDH1 or tDH2 must be met.}
(5) _{If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.}
WRITE CYCLE (T_A = T_OPR, V_CC = 3.3 V)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
tWC
Write cycle time
300
ns
tCW
Chip select to end of write
See Note 1
250
ns
tAW
tAS
tWP
tWR1
tWR2
Address valid to end of write
Address setup time
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
See Note 1
Measured from address valid to beginning of write(2)
Measured from beginning of write to end of write(1)
Measured from WE going high to end of write cycle(3)
Measured from CS going high to end of write cycle(3)
250
ns
56
ns
280
ns
8
ns
25
ns
tDW
tDH1
tDH2
tWZ
tOW
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enable to output high Z
Output active from end of write
Measured to first low-to-high transition of either CS or WE
Measured from WE going high to end of write cycle(4)
Measured from CS going high to end of write cycle(4)
I/O pins are in output state.(5)
I/O pins are in output state.(5)
80
ns
0
ns
15
ns
0
60 ns
0
ns
(1) _{A write cycle ends at the earlier transition of CS going high and WE going high.}
(2) _{A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.}
(3) _{Either tWR1 or tWR2 must be met.}
(4) _{Either tDH1 or tDH2 must be met.}
(5) _{If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.}
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