BQ4802LYPW Datasheet, PDF (10/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR AND EXTERNAL SRAM NONVOLATILE MEMORY BACKUP

bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
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POWER-DOWN/POWER-UP TIMING (T_A = T_OPR)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
tF
VCC slew rate fall time
tR
VCC slew rate rise time
tPF
Interrupt delay time from VPFD
3.0 V to 0 V
300
VSO to VPDF(max)
100
bq4802Y
6
bq4802LY
10
24
40 ^µs
tWPT Write-protect time for external SRAM
bq4802Y See Note 1
bq4802LY See Note 1
90 100 125
150 170 210
tCSR
tRST
tCER
tCED
CS at VHI after power-up
VPFD to RST active (reset active time-out period)
Device enable recovery time
Device enable propagation delay time to external SRAM
bq4802Y
bq4802LY
bq4802Y
bq4802LY
See Note 2
See Note 2
See Note 3
Output load A
100 200 300
170 330 500
tCSR
ms
tCSR
tCSR
tCSR
9
15
ns
15
25
tPBL Push-button low time
1
µs
(1) _{Delay after VCC slews down past VPFD before SRAM is write protected and RST activated.}
(2) _{Internal write-protection period after VCC passes VPFD on power up.}
(3) _{Time during which external SRAM is write protected after VCC passes VPFD on power up.}
CAUTION:NEGATIVE UNDERSHOOTS BELOW THE ABSOLUTE MAXIMUM RATING OF –0.3 V IN BATTERY-
BACKUP MODE MAY AFFECT DATA INTEGRITY.
tF
tR
VCC
VCC
VPFD
2.8
CS
tFS
VSO
tPF
VSO
VPFD(max)
VPFD
tCSR
CEIN
CEOUT
RST
tCED
tWPT
VOHB
tCER
tRST
tCED
INT
High-Z
NOTES: A. PWRIE set to 1 to enable power fail interrupt.
B. RST and INT are open drain and require and external pullup resistor.
Figure 9. Power-Down/Power-Up Timing Diagram
10