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BQ4285E_14 Datasheet, PDF (9/31 Pages) Texas Instruments – Enhanced RTC With NVRAM Control
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bq4285E/L
Control/Status Registers
The four control/status registers of the bq4285E/L are
accessible regardless of the status of the update cycle
(see Table 4).
Register A
Register A Bits
7
6
5
4
3
2
1
0
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
vider. A pattern of 011 behaves as 010 but additionally
transforms register C into a read/write register. This al-
lows the 32.768kHz output on the square wave pin to be
turned on. A pattern of 11X turns the oscillator on, but
keeps the frequency divider disabled. When 010 is writ-
ten, the RTC begins its first update after 500ms.
UIP - Update Cycle Status
7
6
5
4
3
2
1
0
UIP -
-
-
-
-
-
-
Register A programs:
n The frequency of the square-wave and the periodic
event rate.
n Oscillator operation.
Register A provides:
n Status of the update cycle.
RS0–RS3 - Frequency Select
7
6
5
4
3
2
1
0
-
-
-
- RS3 RS2 RS1 RS0
These bits select one of the 13 frequencies for the SQW out-
put and the periodic interrupt rate, as shown in Table 3.
OS0–OS2 - Oscillator Control
7
6
5
4
3
2
1
0
- OS2 OS1 OS0 -
-
-
-
These three bits control the state of the oscillator and di-
vider stages. A pattern of 010 enables RTC operation by
turning on the oscillator and enabling the frequency di-
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
Register B
Register B Bits
7
6
5
4
3
2
UTI PIE AIE UIE SQWE DF
1
0
HF DSE
Register B enables:
n Update cycle transfer operation
n Square-wave output
n Interrupt events
n Daylight saving adjustment
Register B selects:
n Clock and calendar data formats
All bits of register B are read/write.
Table 4. Control/Status Registers
Reg.
A
B
C
D
Loc.
(Hex) Read Write 7 (MSB)
0A Yes Yes1 UIP na
0B Yes Yes UTI na
0C Yes No2 INTF 0
0D Yes No VRT na
6
OS2 na
PIE 0
PF 0
-0
Bit Name and State on Reset
5
4
3
2
OS1 na OS0 na RS3 na RS2 na
AIE 0 UIE 0 SQWE 0 DF na
AF 0 UF 0 - 0 32KE na
-0-0 - 0-0
1
RS1 na
HF na
-0
-0
0 (LSB)
RS0 na
DSE na
-0
-0
Notes:
na = not affected.
1. Except bit 7.
2. Read/write only when OSC2–OSC0 in register A is 011 (binary).
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