BQ4285E_14 Datasheet, PDF (11/31 Pages) Texas Instruments – Enhanced RTC With NVRAM Control

bq4285E/L
Register C
Register C Bits
7
6
5
4
3
2
1
0
INTF PF AF UF
0 32KE 0
0
Register C is the read-only event status register.
Bits 0–3 - Unused Bits
7
6
5
4
3
2
1
0
-
-
-
-
0
-
0
0
INTF - Interrupt Request Flag
7
6
5
4
3
2
1
0
INTF -
-
-
-
-
-
-
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
PIE = 1 and PF = 1
UIE = 1 and UF = 1
Reading register C clears this bit.
These bits are always set to 0.
Register D
32KE–32KHz Enable Output
7
6
5
4
-
-
-
-
3
2
1
0
- 32KE -
-
This bit may be set to a 1 only when the OSC2–OSC0
bits in register A are set to 011. Setting OSC2–OSC0 to
anything other than 011 clears this bit. If SQWE in reg-
ister B and 32KE are set, a 32.768KHz waveform is out-
put on the square wave pin.
Register D Bits
7
6
5
4
3
2
1
0
VRT 0
0
0
0
0
0
0
Register D is the read-only data integrity status register.
Bits 0–6 - Unused Bits
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
0
UF - Update-Event Flag
7
6
5
4
3
-
-
- UF -
2
1
0
-
-
-
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
AF - Alarm Event Flag
7
6
5
4
3
2
1
0
-
- AF -
-
-
-
-
These bits are always set to 0.
VRT - Valid RAM and Time
7
6
5
4
3
2
1
0
VRT -
-
-
-
-
-
-
1 = Valid backup energy source
0 = Backup energy source is depleted
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
PF - Periodic Event Flag
7
6
5
4
3
2
1
0
- PF -
-
-
-
-
-
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
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