ADS8900B Datasheet, PDF (9/76 Pages) Texas Instruments – 20-Bit, High-Speed SAR ADCs With Integrated Reference Buffer, Integrated LDO, and multiSPI Digital Interface

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ADS8900B, ADS8902B, ADS8904B
SBAS728 – NOVEMBER 2016
6.7 Switching Characteristics
At RV_DD = 5.5 V, DV_DD = 1.65 V to 3.6 V, V_REF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at T_A = –40°C to +125°C; typical values at T_A = 25°C.
PARAMETER
MIN
TYP
MAX UNIT
CONVERSION CYCLE
ADS8900B
600
t_conv
Conversion time
ADS8902B
ADS8904B
1100
2400
ASYNCHRONOUS RESET, AND LOW POWER MODES
t_{d_rst}
Delay time: RST rising to RVS rising
t_{PU_ADC}
Power-up time for converter module
1
t_{PU_REFBUF} Power-up time for internal reference buffer, C_REFBUF = 22 µF
10
t_{PU_Device}
Power-up time for
device
C_LDO = 1 µF, C_REFBUF = 22 µF
10
SPI-COMPATIBLE SERIAL INTERFACE
t_{den_CSDO} Delay time: CS falling to data enable
t_{dz_CSDO} Delay time: CS rising to SDO going to Hi-Z
t_{d_CKDO}
Delay time: SCLK launch edge to (next) data valid on SDO
t_{d_CSRDY_f} Delay time: CS falling to RVS falling
t_{d_CSRDY_r}
Delay time:
CS rising to RVS rising
After NOP operation
After WR or RD operation
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)⁽¹⁾
t_{d_CKSTR_r} Delay time: SCLK launch edge to RVS rising
t_{d_CKSTR_f} Delay time: SCLK launch edge to RVS falling
t_{off_STRDO_f} Time offset: RVS falling to (next) data valid on SDO
t_{off_STRDO_r} Time offset: RVS rising to (next) data valid on SDO
t_{ph_STR}
Strobe output high time, 2.35 V ≤ DV_DD ≤ 3.6 V
t_{pl_STR}
Strobe output low time, 2.35 V ≤ DV_DD ≤ 3.6 V
SOURCE-SYNCHRONOUS SERIAL INTERFACE (Internal Clock)
-2
-2
0.45
0.45
t_{d_CSSTR}
t_STR
Delay time: CS falling to RVS rising
Strobe output time
period
INTCLK option
INTCLK / 2 option
INTCLK / 4 option
15
15
30
60
t_{ph_STR}
t_{pl_STR}
Strobe output high time
Strobe output low time
0.45
0.45
(1) The external clock option is not recommended when operating with DV_DD < 2.35 V. See Table 9.
670
1200
ns
2500
3 ms
ms
ms
ms
9
ns
10
ns
13
ns
12
ns
30
ns
120
13
ns
13
ns
2
ns
2
ns
0.55
t_STR
0.55
t_STR
50
ns
ns
0.55
t_STR
0.55
t_STR
TIMING
DIAGRAM
Figure 1
Figure 2
See
PD_CNTL
Register
Figure 3
Figure 4
Figure 4
Figure 4
Figure 5
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