ADS8900B Datasheet, PDF (29/76 Pages) Texas Instruments – 20-Bit, High-Speed SAR ADCs With Integrated Reference Buffer, Integrated LDO, and multiSPI Digital Interface

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ADS8900B, ADS8902B, ADS8904B
SBAS728 – NOVEMBER 2016
Output Data Word D[21:0]
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
FLPAR
D1
FTPAR
D0
XOR
XOR
XOR
XOR
Parity Computation Unit
XOR
XOR
XOR
XOR
)
XOR
11
16 MSBs
10
)
MUX
12 MSBs
01
8 MSBs
00
4 MSBs
PAR_EN
FPAR_LOC[1:0]
Figure 44. Parity Bits Computation
With the PAR_EN bit set to 0, the D[1] and D[0] bits of the output data word are set to 0 (default configuration).
When the PAR_EN bit is set to 1, the device calculates the parity bits (FLPAR and FTPAR) and appends them
as bits D[1] and D[0].
• FLPAR is the even parity calculated on bits D[21:2].
• FTPAR is the even parity calculated on the bits defined by FPAR_LOC[1:0].
See the DATA_CNTL register for more details on the FPAR_LOC[1:0] bit settings.
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