ADS8900B Datasheet, PDF (8/76 Pages) Texas Instruments – 20-Bit, High-Speed SAR ADCs With Integrated Reference Buffer, Integrated LDO, and multiSPI Digital Interface

ADS8900B, ADS8902B, ADS8904B
SBAS728 – NOVEMBER 2016
6.6 Timing Requirements
MIN
TYP
CONVERSION CYCLE
ADS8900B
f_cycle
Sampling frequency
ADS8902B
ADS8904B
ADS8900B
1
t_cycle
ADC cycle-time period ADS8902B
2
ADS8904B
4
t_{wh_CONVST} Pulse duration: CONVST high
30
t_{wl_CONVST} Pulse duration: CONVST low
30
t_acq
Acquisition time
300
t_{qt_acq}
Quiet acquisition time
30
t_{d_cnvcap} Quiet aperture time
20
ASYNCHRONOUS RESET, AND LOW POWER MODES
t_{wl_RST}
Pulse duration: RST low
100
SPI-COMPATIBLE SERIAL INTERFACE
2.35 V ≤ DV_DD ≤ 3.6 V,
T_A = –40°C to +125°C,
V_IH > 0.7 DV_DD, V_IL < 0.3 DV_DD
1.65 V ≤ DV_DD < 2.35 V,
T_A = –40°C to +125°C,
f_CLK
Serial clock frequency
V_IH > 0.8 DV_DD, V_IL < 0.2 DV_DD
1.65 V ≤ DV_DD < 2.35 V,
T_A = 0°C to +60°C,
V_IH > 0.8 DV_DD, V_IL < 0.2 DV_DD
1.65 V ≤ DV_DD < 2.35 V,
T_A = –40°C to +125°C,
V_IH > 0.9 DV_DD, V_IL < 0.1 DV_DD
t_CLK
Serial clock time period
t_{ph_CK}
SCLK high time
t_{pl_CK}
SCLK low time
t_{su_CSCK} Setup time: CS falling to the first SCLK capture edge
t_{su_CKDI}
Setup time: SDI data valid to the SCLK capture edge
t_{ht_CKDI}
Hold time: SCLK capture edge to (previous) data valid on SDI
t_{ht_CKCS} Delay time: last SCLK falling to CS rising
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)⁽¹⁾
1/f_CLK
0.45
0.45
12
1.5
1
7
SDR (DATA_RATE = 0b),
f_CLK
Serial clock frequency ^{2.35 V ≤ DVDD ≤ 3.6 V}
DDR (DATA_RATE = 1b),
2.35 V ≤ DV_DD ≤ 3.6 V
t_CLK
Serial clock time period
1/f_CLK
(1) The external clock option is not recommended when operating with DV_DD < 2.35 V. See Table 9.
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MAX
UNIT
TIMING
DIAGRAM
1000
500 kHz
250
µs
Figure 1
ns
ns
ns
ns
Figure 46,
see Data
ns
Transfer
Protocols
ns
Figure 2
70
20
MHz
57
Figure 3
68
ns
0.55
t_CLK
0.55
t_CLK
ns
ns
ns
ns
Figure 3
Figure 3
70
MHz
35
ns
Figure 4,
see Data
Transfer
Protocols
8
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