ADS58C28IRGCR Datasheet, PDF (9/67 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

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ADS58C28
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
PIN CONFIGURATION (LVDS MODE)
RGC PACKAGE⁽¹⁾
QFN-64
(TOP VIEW)
DRVDD 1
CHB2_M 2
CHB2_P 3
CHB4_M 4
CHB4_P 5
CHB6_M 6
CHB6_P 7
CHB8_M 8
CHB8_P 9
CHB10_M 10
CHB10_P 11
RESET 12
SCLK 13
SDATA 14
SEN 15
AVDD 16
Thermal Pad
(Connected to DRGND)
48 DRVDD
47 CHA4_P
46 CHA4_M
45 CHA2_P
44 CHA2_M
43 CHA0_P
42 CHA0_M
41 NC
40 NC
39 NC
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
(2) The PowerPAD™ is connected to DRGND.
(3) NC = no connection.
Figure 2. ADS58C28 LVDS Pinout
PIN NAME
AVDD
AGND
CLK_P
CLK_M
INA_P
INA_M
INB_P
INB_M
CM
PIN NUMBER
16, 22, 33, 34
17, 18, 21, 24, 27, 28,
31, 32
25
26
29
30
19
20
23
# OF
PINS
4
8
1
1
1
1
1
1
1
Pin Assignments (LVDS Mode)
FUNCTION
Input
Input
Input
Input
Input
Input
Input
Input
Output
Analog power supply
DESCRIPTION
Analog ground
Differential clock positive input
Differential clock negative input
Differential analog positive input, channel A
Differential analog negative input, channel A
Differential analog positive input, channel B
Differential analog negative input, channel B
This pin outputs the common-mode voltage (0.95V) that can be used externally to bias
the analog input pins
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS58C28
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