ADS58C28IRGCR Datasheet, PDF (24/67 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
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Register Address 25h (Default = 00h)
7
6
5
4
3
2
1
0
CH A GAIN
0
CH A TEST PATTERNS
Bits[7:4]
Bit 3
Bits[2:0]
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5dB steps for channel A.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Always write '0'
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A; see Table 12.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern; D[10:0] output data are an alternating sequence of 10101010101 and
01010101010
100 = Outputs digital ramp; output data increments by 1LSB (11 bits) every eighth clock cycle from
code 0 to code 2047
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
7
0
Bit 7
Bits[6:0]
Register Address 26h (Default = 00h)
6
5
4
3
2
1
0
CH A SNRBoost^3G FILTER NUMBER
Always write '0'
CH A SNRBoost^3G FILTER NUMBER: Channel A SNRBoost^3G filter selection
These bits select any one of 55 SNRBoost^3G filters for channel A only after selecting the
appropriate mode from Table 12; refer to the SNR Enhancement Using SNRBoost section.
Register Address 28h (Default = 00h)
7
6
5
4
3
2
1
0
0
CH A SNRBoost^3G ON
0
0
0
0
0
0
Bit 7
Bit 6
Bits[5:0]
Always write '0'
CH A SNRBoost^3G ON: Channel A SNRBoost^3G setting
This bit sets the SNRBoost^3G for channel A
0 = SNRBoost^3G for channel A is off
1 = SNRBoost^3G for channel A is on
Always write '0'
24
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