ADS58C28IRGCR Datasheet, PDF (47/67 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
www.ti.com
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200Ω. Higher impedance can lead to degradation in
performance, compared to the case with 1:1 transformers. For applications where only a band of frequencies are
used, the drive circuit can be tuned to present a low impedance for the sampling glitches. Figure 60 shows an
example with a 1:4 transformer, tuned for a band of approximately 150MHz.
T1
Differential
Input Signal
1:4
Band-Pass
or
Low-Pass
Filter
5W
0.1mF
100W
100W
5W
INx_P
R_IN
C_IN
INx_M
VCM
ADS58C28
Figure 60. Drive Circuit with a 1:4 Transformer
CLOCK INPUT
The ADS58C28 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 61 shows a circuit for the internal clock buffer.
Clock Buffer
L_PKG
2nH
20W
CLK_P
C_BOND
1pF
5kW
C_EQ
C_EQ
R_ESR
100W
2pF
VCM
CLK_M
L_PKG
2nH
C_BOND
1pF
R_ESR
100W
20W
5kW
NOTE: C_EQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 61. Internal Clock Buffer
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