ADS58C28IRGCR Datasheet, PDF (1/67 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
www.ti.com
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
Dual Channel IF Receiver with SNRBoost^3G
Check for Samples: ADS58C28
FEATURES
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•23 Maximum Sample Rate: 200MSPS
• High Dynamic Performance:
– 83dBc SFDR at 140MHz
– 72.5dBFS SNR with 60MHz BW Using
SNRBoost^3G Technology
• SNRBoost^3G Highlights:
– Supports Wide Bandwidth (up to 60MHz)
– Programmable Bandwidths:
20MHz, 30MHz, and 40MHz
– Flat Noise Floor within the Band
– Independent SNRBoost^3G Coefficients for
Both Channels
• Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350mV
– Low Swing: 200mV
– Default Strength: 100Ω termination
– 2x Strength: 50Ω termination
– Compatible with GC6016
– 1.8V Parallel CMOS Interface Also
Supported
• Ultralow Power with Single 1.8V Supply:
– 470mW Total Power
– 710mW Total Power (200MSPS) with
SNRBoost^3G on Both Channels
• Programmable Gain up to 6dB for
SNR/SFDR Trade-off
• DC Offset Correction
• Supports Low Input Clock Amplitude
• Package: QFN-64 (9mm × 9mm)
DESCRIPTION
The ADS58C28 is a dual-channel, 11-bit
analog-to-digital converter (ADC) with sampling rates
up to 200MSPS. The device uses innovative design
techniques to achieve high dynamic performance,
while consuming extremely low power at 1.8V supply.
This architecture makes it well-suited for multi-carrier,
wide bandwidth communications applications.
The ADS58C28 uses third-generation SNRBoost^3G
technology to overcome SNR limitation as a result of
quantization noise (for bandwidths less than Nyquist,
f_S/2). Enhancements in the SNRBoost^3G technology
allow support for SNR improvements over wide
bandwidths (up to 60MHz). In addition, separate
SNRBoost^3G coefficients can also be programmed for
each channel.
The device has a digital gain function that can be
used to improve SFDR performance at lower
full-scale input ranges. It includes a dc offset
correction loop that can be used to cancel the ADC
offset. The digital outputs of all channels are output
as double data rate (DDR) low-voltage differential
signaling (LVDS) together with an LVDS clock output.
The low data rate of this interface (400MBPS at
200MSPS sample rate) makes it possible to use
low-cost field-programmable gate array
(FPGA)-based receivers. The strength of the LVDS
output buffers can be increased to support 50Ω
differential termination. This increase allows the
output clock signal to be connected to two separate
receiver chips with an effective 50Ω termination (such
as the two clock ports of the GC5330). The same
digital output pins can also be configured as a parallel
1.8V CMOS interface.
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS58C28 is
specified over the industrial temperature range
(–40°C to +85°C).
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
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All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated