ADC10DV200 Datasheet, PDF (9/26 Pages) National Semiconductor (TI) – Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs

ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A = V_D = V_DR = +1.8V, f_CLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for T_A = 25°C. Boldface
limits apply for T_MIN ≤ T_A ≤ T_MAX. All other limits apply for T_A = 25°C ^{(1) (2)}
Symbol
Parameter
Conditions
Typical
(3)
Limits
Units
(Limits)
LVDS OUTPUT MODE
Full Operation, Internal Bias
160
mA
I_A
Analog Supply Current
Full Operation, External 3.3kΩ Bias
148
184
mA (max)
I_D
Digital Supply Current
Full Operation
I_DR
Output Driver Supply Current
Power Consumption
Internal Bias
External 3.3kΩ Bias
36
43
mA (max)
64
80
mA (max)
473
mW
450
524
mW (max)
Power Down Power Consumption
CMOS OUTPUT MODE ⁽⁴⁾
PDA=PDB=V_A
57
mW
Full Operation, Internal Bias
138
I_A
Analog Supply Current
Full Operation, External 3.3kΩ Bias
124
mA
I_D
Digital Supply Current
Power Consumption
Full Operation
Internal Bias
External 3.3kΩ Bias
31
mA
310
mW
280
Power Down Power Consumption PDA=PDB=V_A
60
mW
(1) The inputs are protected as shown below. Input voltage magnitudes above V_A or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above V_A or below AGND.
V_A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5V_P-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at T_A = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) CMOS Specifications are for F_CLK = 170 MHz.
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