ADC10DV200 Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs

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ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Figure 24. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source
impedance for the differential inputs will improve even ordered harmonic performance (particularly second
harmonic).
Table 2 indicates the input to output relationship of the ADC10DV200.
V_IN⁺
V_CM − V_REF/2
V_CM − V_REF/4
V_CM
V_CM + V_REF/4
V_CM + V_REF/2
Table 2. Input to Output Relationship
V_IN^−
V_CM + V_REF/2
V_CM + V_REF/4
V_CM
V_CM − V_REF/4
V_CM − V_REF/2
Binary Output
00 0000 0000
01 0000 0000
10 0000 0000
11 0000 0000
11 1111 1111
2’s Complement Output
10 0000 0000
11 0000 0000
00 0000 0000
01 0000 0000
01 1111 1111
Negative Full-Scale
Mid-Scale
Positive Full-Scale
Driving the Analog Inputs
The V_IN+ and the V_IN− inputs of the ADC10DV200 have an internal sample-and-hold circuit which consists of an
analog switch followed by a switched-capacitor amplifier.
Figure 25 and Figure 26 show examples of single-ended to differential conversion circuits. The circuit in
Figure 25 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 26 works well
above 70MHz.
V_{IN 0.1 PF ADT1-1WT}
20:
50:
0.1 PF
18 pF
0.1 PF
20:
V_RM
ADC
Input
Figure 25. Low Input Frequency Transformer Drive Circuit
V_IN
ETC1-1-13
25:
0.1 PF
0.1 PF
25:
ETC1-1-13
0.1 PF
30:
27 pF
30:
V_RM
ADC
Input
Figure 26. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
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