ADC10DV200 Datasheet, PDF (14/26 Pages) National Semiconductor (TI) – Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs

ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
V_INA
V_INB
CLK N
CLK
DRDYA
(DDR)
DA9-DA0
DRDYB
(DDR)
t_AD
CLK N+5
Latency=5.5
CLK Cycles
t_OD
Data N-1
1/f_CLK
t_CH
t_CL
Data N
t_SU
t_H
Data N+1
Data N+2
DB9-DB0
Data N-1
Data N
Data N+1
Figure 2. CMOS Output Timing
Transfer Characteristic
Output Code
1023
1022
MID-SCALE
POINT
512
NEGATIVE
FULL-SCALE
TRANSITION
(V_FS-)
OFFSET
ERROR
POSITIVE
FULL-SCALE
TRANSITION
(V_FS+)
2
1
0
-1 * V_REF
(V_IN +) < (V_IN -)
(V_IN +) > (V_IN -)
0.0V
Analog Input Voltage (V_IN +) - (V_IN -)
Figure 3. Transfer Characteristic
1 * V_REF
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