ADC10DV200 Datasheet, PDF (11/26 Pages) National Semiconductor (TI) – Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs

ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A = V_D = V_DR = +1.8V, f_CLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for T_A = 25°C. Timing measurements
are taken at 50% of the signal amplitude. Boldface limits apply for T_MIN ≤ T_A ≤ T_MAX. All other limits apply for T_A = 25°C ⁽¹⁾
(2)
Symbol
Parameter
Conditions
LVDS OUTPUT MODE
Maximum Clock Frequency
Minimum Clock Frequency
t_CH
Clock High Time
t_CL
Clock Low Time
DCS On
DCS Off
DCS On
DCS Off
DCS On
DCS Off
t_CONV
Conversion Latency
t_ODA
Output Delay of CLK to A-Channel Data
t_ODB
Output Delay of CLK to B-Channel Data
t_SU
Data Output Setup Time
t_H
Data Output Hold Time
t_AD
Aperture Delay
t_AJ
Aperture Jitter
t_SKEW
Data-Data Skew
CMOS OUTPUT MODE ^{(4) (5)}
Maximum Clock Frequency
Minimum Clock Frequency
t_CH
t_CL
t_CONV
t_OD
t_SU
t_H
t_AD
t_AJ
Clock High Time
Conversion Latency
Output Delay of CLK to DATA
Data Output Setup Time⁽⁵⁾
Data Output Hold Time⁽⁵⁾
Aperture Delay
Aperture Jitter
Relative to rising edge of CLK
Relative to falling edge of CLK
Relative to DRDY
Relative to DRDY
DCS On
DCS Off
DCS On
DCS Off
DCS On
DCS Off
Relative to falling edge of CLK
Relative to DRDY
Relative to DRDY
Typical
(3)
Limits
Units
(Limits)
200
MHz (max)
65
45
MHz (min)
1.5
2.4
ns (min)
1.5
2.4
ns (min)
5/5.5
(A/B)
Clock Cycles
2.7
1.46
ns (min)
2.7
1.46
ns (min)
1.2
0.7
ns (min)
1.2
0.7
ns (min)
0.7
ns
0.3
ps rms
20
470
ps
170
MHz
65
25
MHz
1.76
2.82
ns
1.76
2.82
ns
5.5
Clock Cycles
4.5
3.15
ns (min)
5.81
ns (max)
2.5
1.79
ns (min)
3.4
2.69
ns (min)
0.7
ns
0.3
ps rms
(1) The inputs are protected as shown below. Input voltage magnitudes above V_A or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above V_A or below AGND.
V_A
I/O
To Internal Circuitry
AGND
(2) With a full scale differential input of 1.5V_P-P , the 10-bit LSB is 1.465mV.
(3) Typical figures are at T_A = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(4) CMOS Specifications are for F_CLK = 170 MHz.
(5) This parameter is specified by design and/or characterization and is not tested in production.
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