TM4C1236E6PM Datasheet, PDF (888/1234 Pages) Texas Instruments – Tiva Microcontroller

Synchronous Serial Interface (SSI)
For Texas Instruments synchronous serial frame format, the SSInFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSInClk
and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
14.3.4.1
Texas Instruments Synchronous Serial Frame Format
Figure 14-2 on page 888 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
In this mode, SSInClk and SSInFss are forced Low, and the transmit data line SSInTx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSInFss is
pulsed High for one SSInClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSInClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSInTx pin. Likewise, the MSB of the received
data is shifted onto the SSInRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
each falling edge of SSInClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSInClk after the LSB has been latched.
Figure 14-3 on page 889 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
888
June 12, 2014
Texas Instruments-Production Data