TM4C1236E6PM Datasheet, PDF (115/1234 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1236E6PM Microcontroller
3.1.2
3.1.2.1
3.1.2.2
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 67 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 115 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 137 or SWTRIG on page 147.
A pending interrupt remains pending until one of the following:
June 12, 2014
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