TM4C1236E6PM Datasheet, PDF (1098/1234 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
6
5
4
3
2
Name
CLRDT
STALLED
SETUP
FLUSH
ERROR
Type
RW
RW
RW
RW
RW
Reset
0
0
0
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been received.
1 Indicates that a STALL handshake has been received. When
this bit is set, any µDMA request that is in progress is stopped,
the FIFO is completely flushed, and the TXRDY bit is cleared.
Software must clear this bit.
Setup Packet
Value Description
0 No SETUP token is sent.
1 Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Note: Setting this bit also clears the DT bit in the USBTXCSRHn
register.
Flush FIFO
Value Description
0 No effect.
1 Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important: ^{This bit should only be set when the TXRDY bit is clear.}
At other times, it may cause data to be corrupted.
0
Error
Value Description
0 No error.
1 Three attempts have been made to send a packet and no
handshake packet has been received. The TXRDY bit is cleared,
the EPn bit in the USBTXIS register is set, and the FIFO is
completely flushed in this situation.
Software must clear this bit.
Note: This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
1098
Texas Instruments-Production Data
June 12, 2014