TM4C1236E6PM Datasheet, PDF (19/1234 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1236E6PM Microcontroller
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System Control (SYSCTRL), offset 0xD10 ....................................................................... 157
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 159
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 161
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 162
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 163
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 164
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 168
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 174
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 175
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 176
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 177
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 178
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 180
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 181
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 181
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 181
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 181
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 183
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 183
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 183
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 183
Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 186
Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 187
Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 189
Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 190
System Control ............................................................................................................................ 203
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 227
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 229
Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 232
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 233
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 236
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 238
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 241
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 243
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 247
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 249
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 252
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 253
Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 255
Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 257
Register 15: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 258
Register 16: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 259
Register 17: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 260
Register 18: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 261
Register 19: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 263
Register 20: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 265
Register 21: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 267
Register 22: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 268
June 12, 2014
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