TMS570LS3135_17 Datasheet, PDF (86/172 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C – APRIL 2012 – REVISED APRIL 2015
www.ti.com
EMIF_nCS[3:2]
SETUP
STROBE
Extended Due to EMIF_WAIT STROBE HOLD
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
28
25
EMIF_WAIT
2
Asserted
2
Deasserted
Figure 6-16. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements
NO.
MIN
NOM
MAX UNIT
Reads and Writes
E
EMIF clock period
11
ns
2
t_{w(EM_WAIT)}
Pulse duration, EMIFnWAIT
2E
ns
assertion and deassertion
Reads
12
t_{su(EMDV-EMOEH)}
Setup time, EMIFDATA[15:0]
30
ns
valid before EMIFnOE high
13
t_{h(EMOEH-EMDIV)}
Hold time, EMIFDATA[15:0] valid
0.5
ns
after EMIFnOE high
14
t_{su(EMOEL-EMWAIT)}
Setup Time, EMIFnWAIT
4E+30
ns
asserted before end of Strobe
Phase ⁽¹⁾
Writes
28
t_{su(EMWEL-EMWAIT)}
Setup Time, EMIFnWAIT
4E+30
ns
asserted before end of Strobe
Phase ⁽¹⁾
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 6-14 and Figure Figure 6-16 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
Table 6-28. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)
NO.
1
t_{d(TURNAROUND)}
PARAMETER
Turn around time
MIN
Reads and Writes
(TA)*E - 4
Reads
NOM
(TA)*E
MAX UNIT
(TA)*E + 3
ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.
86
System Information and Electrical Specifications
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