TMS570LS3135_17 Datasheet, PDF (61/172 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C – APRIL 2012 – REVISED APRIL 2015
6.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
• Configurable frequency multipliers and dividers.
• Built-in PLL Slip monitoring circuit.
• Option to reset the device on a PLL slip detection.
6.6.1.3.1 Block Diagram
Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
OSCIN
/NR
INTCLK
/1 to /64
PLL
VCOCLK
/OD
/1 to /8
post_ODCLK
/R
/1 to /32
PLLCLK
/NF
/1 to /256
f_PLLCLK = (f_OSCIN / NR) * NF / (OD * R)
OSCIN
/NR2
/1 to /64
INTCLK2
PLL#2
VCOCLK2
/OD2
/1 to /8
post_ODCLK2
/R2
/1 to /32
PLL2CLK
/NF2
/1 to /256
f_PLL2CLK = (f_OSCIN / NR2) * NF2 / (OD2 * R2)
Figure 6-6. ZWT PLLx Block Diagram
6.6.1.3.2 PLL Timing Specifications
f_INTCLK
f_{post_ODCLK}
f_VCOCLK
f_INTCLK2
f_{post_ODCLK2}
f_VCOCLK2
Table 6-11. PLL Timing Specifications
PARAMETER
MIN
PLL1 Reference Clock frequency
1
Post-ODCLK – PLL1 Post-divider input clock frequency
VCOCLK – PLL1 Output Divider (OD) input clock frequency
150
PLL2 Reference Clock frequency
1
Post-ODCLK – PLL2 Post-divider input clock frequency
VCOCLK – PLL2 Output Divider (OD) input clock frequency
150
MAX
20
400
550
20
400
550
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
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System Information and Electrical Specifications
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