TMS570LS3135_17 Datasheet, PDF (76/172 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C – APRIL 2012 – REVISED APRIL 2015
www.ti.com
6.9.4 POM Overlay Considerations
• The POM overlay can map onto up to 8MB of the internal or external memory space. The starting
address and the size of the memory overlay are configurable via the POM module control registers.
Care must be taken to ensure that the overlay is mapped on to available memory.
• ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
• POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
• When POM is used to overlay the flash onto internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
– The POM module implements a time-out feature to detect this exact scenario. The time-out needs
to be enabled whenever POM overlay is enabled.
– The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
– In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
– The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module
is set. If so, then the application can assume that the time-out is caused by a bus contention
between the POM transaction and another master accessing the same memory region. The abort
handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been
caused due to a time-out from the POM.
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System Information and Electrical Specifications
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