TMS570LS3135_17 Datasheet, PDF (1/172 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C – APRIL 2012 – REVISED APRIL 2015
TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Automotive-Grade
Microcontroller for Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– Built-In Self-Test (BIST) for CPU and On-chip
RAMs
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
• ARM^® Cortex^®-R4F 32-Bit RISC CPU
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
– FPU With Single- and Double-Precision
– 12-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
– System Clock up to 180 MHz
– Core Supply Voltage (VCC): 1.2 V Nominal
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
– ADC Supply Voltage (V_CCAD): 3.0 to 5.25 V
• Integrated Memory
– 3MB of Program Flash With ECC (LS3135)
– 2MB of Program Flash With ECC
(LS2135/2125)
– 256KB of RAM With ECC (LS3135/2135)
– 192KB of RAM With ECC (LS2125)
– 64KB of Flash With ECC for Emulated
EEPROM
• 16-Bit External Memory Interface
• Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer OS Timer
– 96-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• Separate Nonmodulating PLL for FlexRay™
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– Parameter Overlay Module (POM)
• Multiple Communication Interfaces
– FlexRay Controller With Two Channels
• 8KB of Message RAM With Parity Protection
• Dedicated Transfer Unit (FTU)
– Three CAN Controllers (DCANs)
• 64 Mailboxes, Each With Parity Protection
• Compliant to CAN Protocol Version 2.0B
– Standard Serial Communication Interface (SCI)
– Local Interconnect Network (LIN) Interface
Controller
• Compliant to LIN Protocol Version 2.1
• Can be Configured as a Second SCI
– Inter-Integrated Circuit (I²C)
– Three Multibuffered Serial Peripheral Interfaces
(MibSPIs)
• 128 Words With Parity Protection Each
– Two Standard Serial Peripheral Interfaces
(SPIs)
• Two Next Generation High-End Timer (N2HET)
Modules
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM Each With Parity
Protection
– Each N2HET Includes Hardware Angle
Generator
– Dedicated High-End Transfer Unit (HTU) With
MPU for Each N2HET
• Two 12-Bit Multibuffered ADC Modules
– ADC1: 24 Channels
– ADC2: 16 Channels Shared With ADC1
– 64 Result Buffers With Parity Protection Each
• General-Purpose Input/Output (GPIO) Pins
Capable of Generating Interrupts
– Sixteen Pins on the ZWT Package
– Four Pins on the PGE Package
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• JTAG Security Module
• Packages
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.