TMS570LS3137_15 Datasheet, PDF (83/173 Pages) Texas Instruments – TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS3137
SPNS162C – APRIL 2012 – REVISED APRIL 2015
The PBIST ROM clock frequency is limited to 90 MHz, if 90 MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 90 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
6.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized to zero via the Memory
Hardware Initialization mechanism in the System module. This hardware mechanism allows an application
to program the memory arrays with error detection capability to a known state based on their error
detection scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the device specific technical reference manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-26.
Table 6-26. Memory Initialization
CONNECTING MODULE
RAM (PD#1)
RAM (RAM_PD#1)
RAM (RAM_PD#2)
RAM (RAM_PD#3)
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
0x08000000
0x0800FFFF
0x08010000
0x0801FFFF
0x08020000
0x0802FFFF
0x08030000
0x0803FFFF
0xFF0A0000
0xFF0BFFFF
0xFF0C0000
0xFF0DFFFF
0xFF0E0000
0xFF0FFFFF
MSINENA REGISTER BIT #
0 ⁽¹⁾
0 ⁽¹⁾
0 ⁽¹⁾
0 ⁽¹⁾
12 ⁽²⁾
11 ⁽²⁾
7 ⁽²⁾
DCAN3 RAM
0xFF1A0000
0xFF1BFFFF
10
DCAN2 RAM
0xFF1C0000
0xFF1DFFFF
6
DCAN1 RAM
FlexRay RAM
0xFF1E0000
0xFF1FFFFF
RAM is not CPU-Addressable
5
n/a ⁽³⁾
MIBADC2 RAM
0xFF3A0000
0xFF3BFFFF
14
MIBADC1 RAM
0xFF3E0000
0xFF3FFFFF
8
N2HET2 RAM
0xFF440000
0xFF45FFFF
15
N2HET1 RAM
0xFF460000
0xFF47FFFF
3
HTU2 RAM
0xFF4C0000
0xFF4DFFFF
16
HTU1 RAM
0xFF4E0000
0xFF4FFFFF
4
DMA RAM
0xFFF80000
0xFFF80FFF
1
VIM RAM
0xFFF82000
0xFFF82FFF
2
RTP RAM
0xFFF83000
0xFFF83FFF
n/a
FTU RAM
0xFF500000
0xFF51FFFF
13
Ethernet RAM (CPPI Memory
Slave)
0xFC520000
0xFC521FFF
n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset
via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system
module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (I) The
module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG
register to become cleared (zero)
(3) Reserved only. The FlexRay RAM has its own initialization mechanism.
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System Information and Electrical Specifications
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