TMS570LS3137_15 Datasheet, PDF (64/173 Pages) Texas Instruments – TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

TMS570LS3137
SPNS162C – APRIL 2012 – REVISED APRIL 2015
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6.6.1.4 External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified in Table 6-12. The external clock
sources are not checked for validity. They are assumed valid when enabled.
PARAMETER
f_EXTCLKx
t_w(EXTCLKIN)H
t_w(EXTCLKIN)L
v_iL(EXTCLKIN)
v_iH(EXTCLKIN)
Table 6-12. External Clock Timing and Electrical Specifications
DESCRIPTION
External clock input frequency
EXTCLK high-pulse duration
EXTCLK low-pulse duration
Low-level input voltage
High-level input voltage
MIN
MAX
80
6
6
-0.3
0.8
2
VCCIO + 0.3
UNIT
MHz
ns
ns
V
V
6.6.2 Clock Domains
6.6.2.1 Clock Domain Descriptions
Table 6-13 lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
CLOCK DOMAIN
NAME
HCLK
GCLK
GCLK2
VCLK
VCLK2
VCLK3
VCLKA1
VCLKA2
Table 6-13. Clock Domain Descriptions
DEFAULT CLOCK
SOURCE
OSCIN
OSCIN
OSCIN
OSCIN
OSCIN
OSCIN
VCLK
VCLK
CLOCK SOURCE
SELECTION
REGISTER
DESCRIPTION
GHVSRC
• Is disabled via the CDDISx registers bit 1
• Used for all system modules including DMA, ESM
GHVSRC
• Always the same frequency as HCLK
• In phase with HCLK
• Is disabled separately from HCLK via the CDDISx registers bit 0
• Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GHVSRC
• Always the same frequency as GCLK
• 2 cycles delayed from GCLK
• Is disabled along with GCLK
• Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
GHVSRC
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 2
GHVSRC
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Frequency must be an integer multiple of VCLK frequency
• Is disabled separately from HCLK via the CDDISx registers bit 3
GHVSRC
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 8
VCLKASRC
• Defaults to VCLK as the source
• Is disabled via the CDDISx registers bit 4
VCLKASRC
• Defaults to VCLK as the source
• Is disabled via the CDDISx registers bit 5
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System Information and Electrical Specifications
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