MSC1200_06 Datasheet, PDF (80/92 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Current-Output Digital Converter (DAC)

MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
Phase Lock Loop High (PLLH)
7
6
5
4
3
SFR F5h
CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK
0
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2
1
0
Reset Value
0
PLL9
PLL8
xxh
CLKSTAT2−0 Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3.
bits 7−5 000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)
101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
PLLLOCK
bit 4
PLL Lock Status and Status Enable.
For Write (PLL Lock Status Enable):
0 = No Effect
1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).
For Read (PLL Lock Status):
0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode)
1 = PLL Locked (PLL is active clock).
PLL9−8
bits 1−0
PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h).
Analog Clock (ACLK)
7
SFR F6h
0
6
FREQ6
5
FREQ5
4
FREQ4
3
FREQ3
2
FREQ2
1
FREQ1
0
FREQ0
FREQ6−0
bits 6−0
Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock.
f_ACLK
+
f_CLK
ACLK )
1
,
where
f_CLK
+
f_OSC
SYSCLK divider
.
f_MOD
+
f_ACLK
64
ADC
Data
Rate
+
f_DATA
+
f_MOD
Decimation
Ratio
Reset Value
03h
System Reset (SRST)
7
6
5
4
3
2
1
0
Reset Value
SFR F7h
0
0
0
0
0
0
0
RSTREQ
00h
RSTREQ Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.
bit 0
80