MSC1200_06 Datasheet, PDF (3/92 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Current-Output Digital Converter (DAC)

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MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
ELECTRICAL CHARACTERISTICS: AV_DD = 5V
All specifications from T_MIN to T_MAX, DV_DD = +2.7V to +5.25V, f_MOD = 15.625kHz, PGA = 1, Buffer ON, f_DATA = 10Hz, ADC Bipolar Mode, and
V_REF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted.
MSC120x
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Analog Input (AIN0-AIN5, AINCOM)
Analog Input Range
Full-Scale Input Voltage Range
Differential Input Impedance
Buffer OFF
Buffer ON
(In+) − (In−), Bipolar Mode
Buffer OFF
AGND − 0.1
AV_DD + 0.1
V
AGND + 50mV
AV_DD − 1.5
V
±V_REF/PGA
V
7/PGA⁽¹⁾
MΩ
Input Current
Buffer ON
0.5
nA
Fast Settling Filter
Bandwidth
Sinc² Filter
Sinc³ Filter
Programmable Gain Amplifier
−3dB
−3dB
−3dB
User-Selectable Gain Range
0.469 • f_DATA
0.318 • f_DATA
0.262 • f_DATA
1
128
Input Capacitance
Buffer ON
7
pF
Input Leakage Current
Multiplexer Channel OFF, T = +25°C
0.5
pA
Burnout Current Sources
Buffer ON
±2
µA
ADC Offset DAC
Offset DAC Range
Offset DAC Resolution
±V_REF/(2 •PGA)
V
8
Bits
Offset DAC Full-Scale Gain Error
±1.0
% of Range
Offset DAC Full-Scale Gain Error Drift
0.6
ppm/°C
System Performance
MSC1200, MSC1201
24
Bits
Resolution
MSC1202
16
Bits
ENOB
MSC1200, MSC1201
MSC1202
22
Bits
16
Bits
Output Noise
See Typical Characteristics
MSC1201, Sinc³ Filter, Decimation > 360
24
Bits
No Missing Codes
MSC1202, Sinc³ Filter
16
Bits
Integral Nonlinearity
End Point Fit, Differential Input
±0.0004
±0.0015
% of FSR
Offset Error
After Calibration
1.5
ppm of FS
Offset Drift⁽²⁾
Before Calibration
0.1
ppm of FS/°C
Gain Error⁽³⁾
After Calibration
0.005
%
Gain Error Drift⁽²⁾
Before Calibration
0.5
ppm/°C
System Gain Calibration Range
80
120
% of FS
System Offset Calibration Range
−50
50
% of FS
At DC, V_IN = 0V
120
dB
Common-Mode Rejection
f_CM = 60Hz, f_DATA = 10Hz
f_CM = 50Hz, f_DATA = 50Hz
130
dB
120
dB
f_CM = 60Hz, f_DATA = 60Hz
120
dB
Normal-Mode Rejection
f_CM = 50Hz, f_DATA = 50Hz
f_CM = 60Hz, f_DATA = 60Hz
100
dB
100
dB
Power-Supply Rejection
At DC, dB = −20log(∆V_OUT/∆V_DD)⁽⁴⁾, V_IN = 0V
100
dB
(1) _{The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).}
(2) _{Calibration can minimize these errors.}
(3) _{The gain self-calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.}
(4) _{∆VOUT is change in digital result.}
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