LMH0036 Datasheet, PDF (8/19 Pages) National Semiconductor (TI) – SD SDI Reclocker with 4:1 Input Multiplexer

LMH0036
SNLS254B – MARCH 2008 – REVISED APRIL 2013
V_CC
20 k:
1 pF
80 k:
V_CC
2 k:
2 k:
V_CC
SDI[3:0]
SDI[3:0]
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Figure 2. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0])
V_CC
V_CC
50: 50:
V_CC
SDO, SCO/SDO2
SDO, SCO/SDO2
Figure 3. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second
retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being
processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the
corresponding serial data bit interval within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low
level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The
SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2
enabled). SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is
activated and this output is functioning as a serial clock output, the output will also be muted. If an unsupported
data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the output is
invalid.
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