LMH0036 Datasheet, PDF (6/19 Pages) National Semiconductor (TI) – SD SDI Reclocker with 4:1 Input Multiplexer

LMH0036
SNLS254B – MARCH 2008 – REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.⁽¹⁾
Symbol
Parameter
Conditions
Reference
Min
BR_SD
TOL_JIT
TOL_JIT
t_JIT
BW_LOOP
Serial Data Rate
Serial Input Jitter
Tolerance
Serial Input Jitter
Tolerance
Serial Data Output Jitter
Loop Bandwidth
SMPTE 259M (C)
270 Mbps ^{(2) (3) (4)}
270 Mbps ^{(2) (3) (5)}
270 Mbps⁽³⁾⁽⁶⁾
270 Mbps,
<0.1dB Peaking
SDI, SDO
SDI
SDI
SDO
>6
>0.6
F_CO Serial Clock Output
Frequency
270 Mbps data rate
SCO
t_JIT
Serial Clock Output Jitter
Serial Clock Output
Alignment with respect to
Data Interval
SDO, SCO
40
T_ACQ
t_r, t_f
t_r, t_f
t_r, t_f
t_r, t_f
F_REF
Serial Clock Output Duty
Cycle
Acquisition Time
Input rise/fall time
Input rise/fall time
Output rise/fall time
Output rise/fall time
Reference Clock
Frequency
See ^{(7) (8)}
10%–90%
20%–80%
10%–90%
20%–80% ⁽⁹⁾
SCO
45
Logic inputs
SDI
Logic outputs
SCO, SDO
F_TOL
Ref. Clock Freq.
Tolerance
Typ
270
0.02
300
270
2
1.5
1.5
90
27
±50
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Max
0.08
3
60
55
15
3
1500
3
130
Units
Mbps
UI_P-P
UI_P-P
UI_P-P
kHz
MHz
ps_RMS
%
%
ms
ns
ps
ns
ps
MHz
ppm
(1) Typical values are stated for: V_CC = +3.3V, T_A = +25°C.
(2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
(3) This parameter is ensured by characterization over voltage and temperature limits.
(4) Refer to “A1” in Figure 1 of SMPTE RP 184-1996.
(5) Refer to “A2” in Figure 1 of SMPTE RP 184-1996.
(6) Serial Data Output Jitter is total output jitter with 0.2UI_P-P input jitter.
(7) Specification is ensured by design.
(8) Measured from first SDI transition until Lock Detect (LD) output goes high (true).
(9) R_L = 100Ω differential.
6
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