DS90LV110T_14 Datasheet, PDF (8/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor

DS90LV110T
SNOS522I – JANUARY 2001 – REVISED APRIL 2013
www.ti.com
For applications operating at data rate greater than 400Mbps, a point-to-point distribution application should be
used. This improves signal quality compared to multi-drop applications due to no stub PCB trace loading. The
only load is a receiver at the far end of the transmission line. Point-to-point distribution applications will have a
wider LVDS bus lines, but data rate can increase well above 400Mbps due to the improved signal quality.
Pin Name
IN+
IN -
OUT+
OUT -
EN
V_SS
V_DD
# of Pin
1
1
10
10
1
3
2
PIN DESCRIPTIONS
Input/Output
Description
I
Non-inverting LVDS input
I
Inverting LVDS input
O
Non-inverting LVDS Output
O
Inverting LVDS Output
I
This pin has an internal pull-down when left open. A logic low on the
Enable puts all the LVDS outputs into TRI-STATE and reduces the
supply current.
P
Ground (all ground pins must be tied to the same supply)
P
Power Supply (all power pins must be tied to the same supply)
INPUT INTERFACING
The DS90LV110 accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the DS90LV110 can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML).
Figure 10, Figure 11, and Figure 12 illustrate typical DC-coupled interface to common differential drivers.
LVDS
Driver
OUT+
100: Differential T-Line
DS90LV110
Receiver
IN+
100:
OUT-
IN-
Figure 10. Typical LVDS Driver DC-Coupled Interface to DS90LV110 Input
CML3.3V or CML2.5V
Driver
V_CC
50:
50:
OUT+
100: Differential T-Line
DS90LV110
Receiver
IN+
100:
OUT-
IN-
Figure 11. Typical CML Driver DC-Coupled Interface to DS90LV110 Input
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