DS90LV110T_14 Datasheet, PDF (7/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor

DS90LV110T
www.ti.com
SNOS522I – JANUARY 2001 – REVISED APRIL 2013
The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding
and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be
effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via
placement also improves signal integrity on signal transmission lines by providing short paths for image currents
which reduces signal distortion. The planes should be pulled back from all transmission lines and component
mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric
separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so
minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component
mounting pads.
There are more common practices which should be followed when designing PCBs for LVDS signaling. Please
see Application Note: AN-1108(SNLA008) for additional information.
Multi-Drop Applications
Figure 8. Multi-Drop Applications
Point-to-Point Distribution Applications
Figure 9. Point-to-Point Distribution Applications
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