DS90LV110T_14 Datasheet, PDF (2/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor

DS90LV110T
SNOS522I – JANUARY 2001 – REVISED APRIL 2013
Block Diagram
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Figure 1. Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings ⁽¹⁾
Supply Voltage (V_DD-V_SS)
LVCMOS/LVTTL Input Voltage (EN)
LVDS Receiver Input Voltage (IN+, IN−)
LVDS Driver Output Voltage (OUT+, OUT−)
Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 sec.)
Maximum Package Power Dissipation at 25°C
28 Lead TSSOP
Package Derating
28 Lead TSSOP
θ_JA (4-Layer, 2 oz. Cu, JEDEC)
28 Lead TSSOP
ESD Rating:
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
−0.3V to +4V
−0.3V to (V_CC + 0.3V)
−0.3V to +4V
−0.3V to +4V
+150°C
−65°C to +150°C
+260°C
2.115 W
16.9 mW/°C above +25°C
59.1 °C/Watt
> 4 kV
> 250 V
(1) “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. Electrical Characteristics provides conditions for actual device operation.
2
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